The present invention relates to an interrupt controller preferably used to provide a microcomputer capable of implementing multiple interrupt, and also relates to a microcomputer incorporating this interrupt controller.
In addition to a CPU and memories, a general microcomputer is associated with peripheral circuits, such as an A/D converter, a timer, and a PWM (pulse width modulation) waveform generating circuit. In transmitting data from the CPU to these peripheral circuits and in receiving the data from these peripheral circuits to the CPU, interrupt is used as one interfacial means. A high-performance microcomputer is usually associated with a plurality of peripheral circuits each sending an interrupt request to the CPU. In such a case, there is a possibility that the high-performance microcomputer simultaneously receives a plurality of interrupt requests. To manage such overlapping of interrupt requests, the high-performance microcomputer comprises an interrupt controller interposed between the CPU and each of the peripheral circuits.
For example, the interrupt controller operates in synchronism with the CPU under a same or common clock. The interrupt controller collectively administrates all of the interrupt requests. The interrupt controller arranges these multiple interrupt requests into one signal, which is an interrupt request signal sent to the CPU. This interrupt request signal is hereinafter referred to as a CPU interrupt request signal which differs from an interrupt request signal sent from each peripheral circuit to the CPU. The CPU has an interrupt input terminal receiving the CPU interrupt request signal thus outputted from the interrupt controller.
More specifically, when the interrupt controller receives a plurality of interrupt request signals simultaneously from peripheral circuits, the interrupt controller selects an interrupt request having a highest priority. Then, the interrupt controller produces a vector address corresponding to the selected interrupt processing. Meanwhile, the interrupt controller sends the above-described CPU interrupt request signal to the CPU. When the CPU receives the CPU interrupt request signal, the CPU waits for a delay time which is required for the CPU to prepare the interrupt. After the delay time has passed, the CPU sends a response signal to the interrupt controller. The response signal indicates that the preparation for the interrupt has been accomplished. At the same time, the CPU reads the vector address produced from the interrupt controller. Then, the CPU executes the interrupt processing which is stored in an area designated by this vector address.
In this manner, the interrupt controller outputs the CPU interrupt request signal to cause the CPU to implement the interrupt processing requested by the peripheral circuit. When the CPU is presently implementing other interrupt processing, it is necessary to make the CPU suspend the presently running interrupt processing. However, if the CPU automatically suspends every interrupt processing being presently executed in response to each CPU interrupt request signal sent from the interrupt controller, there will be a possibility that the suspended interrupt processing may have a priority higher than that of the interrupt processing designated by the entered CPU interrupt request signal.
Accordingly, in performing the conventional multiple interrupt, the interrupt controller compares the priority of the interrupt processing presently running in the CPU with the priority of the interrupt processing requested by the peripheral circuit. Then, the interrupt controller sends the CPU interrupt request signal to the CPU only when the priority of the interrupt processing requested by the peripheral circuit is higher than the priority of the interrupt processing presently running in the CPU.
However, in comparing the priority of the interrupt processing presently running in the CPU with the priority of the interrupt processing requested by the peripheral circuit, it is definitely necessary for the interrupt controller to recognize the priority of the interrupt processing presently running in the CPU. To this end, the conventional CPU administrates (memorizes) the priority of the interrupt processing presently running in the CPU. When the interrupt controller receives an interrupt request from a peripheral circuit, the interrupt controller receives the priority of the presently running interrupt processing from the CPU and compares it with the priority of the interrupt processing requested by the peripheral circuit.
Meanwhile, when the CPU receives the CPU interrupt request signal from the interrupt controller during execution of the interrupt processing, the CPU suspends the presently running interrupt processing. The CPU temporarily transfers (i.e., stacks) the data necessary in restarting the suspended interrupt processing to an external storage medium, such as RAM. The processing data necessary in restarting the suspended interrupt processing is, for example, a program counter value and a flag processing state or the like. Similarly, the CPU transfers (i.e., stacks) the level information representing the priority of the suspended interrupt processing to the same external storage medium. Thereafter, the CPU executes the newly request interrupt processing in accordance with the vector address read out from the interrupt controller. When the requested interrupt processing is accomplished, the CPU obtains the stacked information from the external storage medium and restarts the suspended interrupt processing based on the obtained information.
As described above, according to the conventional microcomputer executing the multiple interrupt to the CPU, the CPU itself manages (memorizes) the priority of the interrupt processing being presently executed in the CPU. Accordingly, when the CPU suspends the presently running interrupt processing, the CPU temporarily transfers (stacks) the information necessary in restarting the suspended interrupt processing into RAM or a comparable storage medium. In this case, in addition to the information necessary to restart the suspended interrupt processing, the CPU can transfer (stack) the priority of the suspended interrupt processing into the same storage medium. Thus, administrating the priority of the suspended interrupt processing can be easily done by the CPU.
However, to possess such a priority administrating function, the CPU needs to have a component (i.e., register) which stores the priority of the presently running interrupt processing. This significantly enlarges the circuit scale of the CPU.
In some cases, a same spec CPU may be commonly used in constituting a microcomputer requiring no multiple interrupt and in constituting a microcomputer requiring the multiple interrupt. In such cases, if the commonly used CPU has the above-described priority storing register, the circuit scale of the CPU will be too much large for the microcomputer requiring no multiple interrupt. An effective downsizing cannot be realized for this microcomputer. Furthermore, in this case, for the microcomputer requiring no multiple interrupt, its cost unnecessarily increases due to use of the CPU having unnecessary functions.
To enhance the usability of CPU, it is necessary to enlarge the capacity of the register (in other words, the bit number of the register) so that all of the priority data can be stored in the register even if a large number of interrupt requests are generated from peripheral circuits and the data length (i.e., bit number) of the priority being set for each interrupt request becomes large. Accordingly, if required to use a same conventional CPU for various microcomputers whose purposes are different from each other, the circuit scale of this conventional CPU needs to become large. In other words, the microcomputer cannot be downsized.
The present invention has an object to provide an interrupt controller which makes it possible to use a same or common spec CPU for various microcomputers regardless of implementation of multiple interrupt in these microcomputers, and also has an object to suppress functions of CPU to an allowable minimum level to reduce the circuit scale of CPU. Furthermore, the present invention has an object to provide a microcomputer incorporating this interrupt controller.
In order to accomplish the above and other related objects, the present invention provides a novel interrupt controller. The interrupt controller of the present invention is similar to the above-described conventional interrupt controller in that:
the interrupt controller is responsive to an interrupt request entered from a peripheral circuit;
the interrupt controller compares a priority of the entered interrupt request with a priority of interrupt processing presently running in the CPU;
the interrupt controller outputs an interrupt request signal (i.e., CPU interrupt request signal) to the CPU when the priority of the entered interrupt request is higher than the priority of the interrupt processing presently running in the CPU;
the interrupt controller receives a response signal from the CPU after the interrupt request signal is produced, the response signal representing completion of interrupt preparation in the CPU; and
the interrupt controller outputs an interrupt identification data to the CPU directly or indirectly via an external interrupt identification data transmitting means, so as to cause the CPU to execute interrupt processing designated by the interrupt request.
Furthermore, the interrupt controller of the present invention comprises a level information storing/renewing means which is responsive to the interrupt request signal sent to CPU to store level information representing the priority of the interrupt processing presently running in the CPU. When the interrupt processing presently running in the CPU is suspended in response to the interrupt request signal, the level information storing/renewing means temporarily transfers the level information of the suspended interrupt processing to a predetermined area of a storage medium. When the CPU restarts the suspended interrupt processing, the level information storing/renewing means reads the level information of the suspended interrupt processing from the storage medium and renews presently stored level information by the readout level information.
Namely, the interrupt controller of the present invention is characterized in that the level information storing/renewing means is provided for enabling the interrupt controller to administrate the level information (i.e., priority of the interrupt processing presently running in the CPU) which is conventionally administrated (memorized) in the CPU.
Accordingly, using the interrupt controller of the present invention allows the CPU to exclude a storage (i.e., register) for storing the priority of the interrupt processing presently running in the CPU. The circuit scale of the CPU can be reduced. Therefore, when a same spec CPU is commonly used in constituting a small-sized microcomputer requiring no multiple interrupt and a large-sized microcomputer requiring the multiple interrupt, the present invention can attain both downsizing and cost-reduction for the small-sized microcomputer which requires no multiple interrupt.
According to the present invention, it is preferable that the level information storing/renewing means comprises a level information storing section (e.g., register etc.) which stores the level information of the interrupt processing presently running in the CPU. In general, the information amount storable in the level information storing section (in other words, the capacity of the level information storing section) should be sufficient enough to surely store the level information being set in accordance with the type of the interrupt request generated from each peripheral circuit. The information amount may be set to a value sufficiently large compared with the data length of the level information.
However, this will enlarge the size of the interrupt controller. Therefore, a microcomputer employing this interrupt controller cannot be downsized.
Hence, according to a preferred embodiment of the present invention, it is desirable that the information amount storable in the level information storing section (e.g., a register) provided in the level information storing/renewing means is determined in accordance with the data length of the level information being set in accordance with each interrupt request generated from the peripheral circuit. With this arrangement, it becomes possible to minimize the capacity of level information storing section provided in the level information storing/renewing means. Thus, the present invention attains the downsizing of the interrupt controller, and accordingly attains the downsizing of the microcomputer incorporating this interrupt controller.
Namely, the interrupt controller of the present invention can administrate the priority of the interrupt processing by itself, whereas it was conventionally done by the CPU. Thus, the present invention makes it possible to constitute various microcomputers by using a general purpose CPU which possesses no function of administrating the priority of the interrupt processing. Furthermore, the present invention makes it possible to set an adequate capacity for the level information storing section so that a minimum sized microcomputer can execute interrupt processing by using a general purpose CPU.
Meanwhile, the interrupt controller receives the response signal representing completion of interrupt preparation in the CPU. The interrupt controller outputs the interrupt identification data to the CPU directly or indirectly via the external interrupt identification data transmitting means. The interrupt identification data can be any information as long as it can identify the interrupt request sent from each peripheral circuit. For example, the interrupt identification data may be a predetermined signal pattern. According to the preferred embodiment of the present invention, it is desirable that the interrupt identification data is a vector address corresponding to an interrupt processing routine performed in the CPU. This makes it possible for the CPU to execute the interrupt processing by simply storing the vector address into a program counter. Hence, the CPU can promptly start the interrupt processing.
Furthermore, the present invention provides a microcomputer comprising the above-described interrupt controller, the CPU implementing the designated interrupt processing in response to the interrupt request sent from the interrupt controller, and a plurality of peripheral circuits, each sending an interrupt request to the interrupt controller. According to the microcomputer of the present invention, when the peripheral circuit generates an interrupt request, the priority of this interrupt request is compared with the priority of an interrupt processing presently running in the CPU. When the priority of the requested interrupt request is higher than the priority of the presently running interrupt processing, the CPU suspends the presently running interrupt processing and executes the requested interrupt request corresponding to the interrupt request generated by the peripheral circuit. The microcomputer of the present invention can implement the multiple interrupt.
In general, in this kind of the microcomputers capable of implementing the multiple interrupt, the CPU executes a general interrupt exceptional processing (program) in response to an interrupt request signal (i.e., a CPU interrupt request signal) sent from the interrupt computer. By executing this general interrupt exceptional processing, the CPU suspends the interrupt processing presently running therein. The processing data (for example, a program counter value and a flag processing state or the like) required in restarting the suspended processing is temporarily transferred (stacked) into an external storage medium such as RAM. Thereafter, after accomplishing the interrupt processing corresponding to the CPU interrupt request signal, the CPU executes a general interrupt recovery processing (program). Through this general interrupt recovery processing, the CPU reads the stacked processing data from the external storage medium. Then, the CPU restarts the suspended interrupt processing. According to the present invention, the interrupt controller comprises the level information storing/renewing means which performs the transferring (i.e., stacking) operation and the reading operation of the level information in synchronism with the above-described operation of the CPU.
Accordingly, in the microcomputer of the present invention, the interrupt controller implements the multiple interrupt to the CPU. Like the conventional microcomputer, after accomplishing new interrupt processing, the microcomputer of the present invention can restart the suspended interrupt processing. The timings for transferring (stacking) and reading the processing data in the CPU may be set to be different from the timings for transferring (stacking) and reading the level information in the interrupt controller. This elongates the time required for starting the new interrupt processing or restarting the suspended interrupt processing.
Accordingly, to eliminate the above-described problem, the preferred embodiment of the present invention proposes a preferable arrangement for the CPU and the level information storing/renewing means in the interrupt controller.
Namely, according to the microcomputer disclosed in the preferred embodiment of the present invention, the CPU implements interrupt exceptional processing. In this interrupt exceptional processing, the CPU suspends the interrupt processing presently running therein when the CPU receives an interrupt request signal from the interrupt controller, the CPU sends a stack instruction to the interrupt controller while transferring processing data to an external storage medium, the processing data being necessary in restarting the suspended interrupt processing, and the interrupt controller transfers the level information stored in the level information storing/renewing means to the external storage medium, thereby simultaneously stacking the processing data and the level information in the same storage medium.
Furthermore, in the microcomputer disclosed in the preferred embodiment of the present invention, the CPU implements the interrupt recovery processing in which the CPU restarts the suspended interrupt processing upon accomplishing the designated interrupt processing, wherein the CPU reads the processing data from the external storage medium while generating a return instruction to the interrupt controller, thereby causing the level information storing/renewing means to read the level information from the external storage medium in synchronism with the reading of the processing data by the CPU.
Meanwhile, in the interrupt controller, the level information storing/renewing means performs the transferring and reading of the level information to and from the external storage medium when the level information storing/renewing means receives the stack instruction and the return instruction from the CPU.
Therefore, according to the microcomputer disclosed in the preferred embodiment of the present invention, the timings for transferring (stacking) and reading the level information in the interrupt controller can be equalized with the timings for transferring and reading the processing data in the CPU. Thus, these data can be simultaneously transferred (stacked) into a same storage medium such as RAM, and simultaneously read out from this storage medium. Hence, it becomes possible for the CPU to shorten the time required for starting the new interrupt processing corresponding to the multiple interrupt or restarting the suspended interrupt processing.